This invention relates to a thin film static induction transistor and a method for manufacturing the same.
In recent years, active research work is performed on the method of fabricating numerous active devices within a thin spacious semiconductor film. These devices are applied, for example, as image sensors of an image input device, or thin film transistors for driving a display panel in a liquid crystal television system. Since the above-mentioned active devices are demanded to carry out a high speed operation, the method of manufacturing high speed TFTs (thin film transistors) is now raised as a problem. For the resolution of the problem, various types of MOS TFT have been developed by introducing CVD (chemical vapor deposition) or sputtering. For example, an MOS TFT prepared from amorphous semiconductor such as amorphous silicon or another type of MOS TFT consisting of polycrystalline silicon has been developed. However, the MOS type TFT prepared from the above-mentioned amorphous silicon has an operation frequency of the order of 200 KHz, and the MOS type TFT consisting of the aforesaid polycrystalline silicon has an operation frequency of 1 to 2 MHz. In recent years, active devices formed within a thin semiconductor film are demanded to be operated with a frequency of 5 to 10 MHz. Moreover, it is desired to manufacture active devices like MOS type TFTs by a low temperature process. From the above-mentioned point of view, the MOS type TFT prepared from amorphous silicon has the drawback that the operation frequency is small, though it is adapted for the low temperature manufacture. Another MOS type TFT prepared from polycrystalline silicon has the drawbacks that since it has to be fabricated at a high temperature such as at least 500.degree. C., it is not only unsuitable for the low temperature manufacture but also fails to have its operation frequency increased up to the desired level.
Under the aforementioned circumstances, a thin film static induction transistor has been developed whose operation frequency can be accelerated up to a level of several MHz. Description may now be made with reference to FIG. 1 of the typical structure of the developed device. An n type amorphous silicon layer 2 acting as a drain electrode is deposited on insulative substrate 1 prepared from, for example, a glass plate. Provided on the layer 2 is intrinsic amorphous silicon layer 3 acting as an electron-travelling region. Shottky gate electrodes 4 are provided within the layer 3 at an equal distance. Further formed on the layer 3 are amorphous silicon layers 5 acting as source electrodes. The source electrodes 5 are so positioned as to face an intervening space between every two Shottky gate electrodes 4. In other words, electrodes 4 and amorphous silicon layers 5 are arranged in the staggered fashion in order to decrease capacitances between the respective gate electrodes 4 and source electrodes 5. Layer 3a is first formed to embed gate electrodes 4 in layer 3 as illustrated in FIG. 1. Gate electrodes 4 are formed on the layer 3a. Then layer 3b is further formed on the layer 3a.
The conventional SIT illustrated in FIG. 1 is accompanied with the undermentioned drawbacks. To begin with, electron traveling region 3 or channel region is prepared from intrinsic amorphous silicon, and has a high resistance of the order of 10.sup.9 .OMEGA.cm. Now let it be assumed that layer 3b acts as an electron injection region. Since, in FIG. 1, no care is taken with respect to the conductivity of the electron injection region. Region 3b, too, has as high a resistance as 10.sup.9 .OMEGA.cm. Consequently, drain current Ids flowing through an area defined between source and drain regions decreases due to the negative feed back action. Namely, the conventional device failed to fully increase drain current Ids. In the second place, an interface region is produced between layers 3a, 3b. Since the interface region deteriorates the control of drain current Ids by gate electrodes, the dynamic range of the drain current decreases. In the third place, the distance between the respective gate electrodes is of the order of 1-5 microns. However, tremendous difficulties are encountered in realizing the above-mentioned staggered arrangement by the present photo-etching technique with such an extremely high precision as less than 1 micron.